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Intel C++ Compiler, is a group of C, C++, SYCL and Data Parallel C++ (DPC++) compilers from Intel available for Windows, Mac, Linux, and FreeBSD.^[3]

Overview[edit]

The compilers generate code for IA-32 and Intel 64 architectures, including compatible processors from AMD. A specific release of the compiler (11.1) is available for development of Linux-based applications for IA-64 (Itanium 2) processors.

The 2021 oneAPI release^[4] added the ability to generate optimized code for Intel GPUs and FPGAs. Intel compilers support SYCL, initial OpenMP 5.1, symmetric multiprocessing, automatic parallelization, and Guided Auto-Parallelization (GAP). With the add-on Cluster OpenMP capability, the compilers can also automatically generate Message Passing Interface calls for distributed memory multiprocessing from OpenMP directives.

DPC++^[5][6] builds on the SYCL specification from The Khronos Group. It is designed to allow developers to reuse code across hardware targets (CPUs and accelerators such as GPUs and FPGAs) and perform custom tuning for a specific accelerator. DPC++ = C++17 and SYCL and open source community extensions that make SYCL easier to use. Many of these extensions were adopted by the SYCL 2020 provisional specification^[7] including unified shared memory, group algorithms and sub-groups.

The Intel compilers are compatible with Microsoft Visual C++ on Windows and integrate into Microsoft Visual Studio. On Linux and Mac, they are compatible with GNU Compiler Collection (GCC) and the GNU toolchain. Intel compilers are known for the application performance they can enable as measured by benchmarks, such as the SPEC CPU benchmarks.

Optimizations[edit]

Intel compilers are optimized for computer systems using processors that support Intel architectures. They are designed to minimize stalls and to produce code that executes in the fewest possible number of cycles. The Intel C++ Compiler supports three separate high-level techniques for optimizing the compiled program: interprocedural optimization (IPO), profile-guided optimization (PGO), and high-level optimizations (HLO). The Intel C++ compiler in the Parallel Studio XE products also supports tools, techniques and language extensions for adding and maintaining application parallelism on IA-32 and Intel 64 processors and enables compiling for Intel Xeon Phi processors and coprocessors.

Profile-guided optimization refers to a mode of optimization where the compiler is able to access data from a sample run of the program across a representative input set. The data would indicate which areas of the program are executed more frequently, and which areas are executed less frequently. All optimizations benefit from profile-guided feedback because they are less reliant on heuristics when making compilation decisions.

High-level optimizations are optimizations performed on a version of the program that more closely represents the source code. This includes loop interchange, loop fusion, loop fission, loop unrolling, data prefetch, and more.^[8]

Interprocedural optimization applies typical compiler optimizations (such as constant propagation) but using a broader scope that may include multiple procedures, multiple files, or the entire program.^[9]

David Monniaux has criticized Intel's compiler for applying, by default, floating-point optimizations which are not allowed by the C standard and which require special flags with other compilers such as gcc.^[10]

Architectures[edit]

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• x86-64 (Intel 64 and AMD64)
• IA-64 (Itanium 2)

Description of packaging[edit]

The compilers are available standalone from Intel APT and Yum repositories. They are also available in the Intel oneAPI Base Toolkit which includes other build tools, such as libraries, and analysis tools for error checking and performance analysis. Containers with the compilers are on Docker Hub.

History since 2003[edit]

Flags and manuals[edit]

Documentation can be found at the Intel Software Technical Documentation site.

Debugging[edit]

The Intel compiler provides debugging information that is standard for the common debuggers (DWARF 2 on Linux, similar to gdb, and COFF for Windows). The flags to compile with debugging information are /Zi on Windows and -g on Linux. Debugging is done on Windows using the Visual Studio debugger and, on Linux, using gdb.

While the Intel compiler can generate a gprof compatible profiling output, Intel also provides a kernel level, system-wide statistical profiler called Intel VTune Profiler. VTune can be used from a command line or thru an included GUI on Linux or Windows. It can also be integrated into Visual Studio on Windows, or Eclipse on Linux). In addition to the VTune profiler, there is Intel Advisor that specializes in vectorization optimization, offload modeling, flow graph design and tools for threading design and prototyping.

Intel also offers a tool for memory and threading error detection called Intel Inspector XE. Regarding memory errors, it helps detect memory leaks, memory corruption, allocation/de-allocation of API mismatches and inconsistent memory API usage. Regarding threading errors, it helps detect data races (both heap and stack), deadlocks and thread and synch API errors.

Reception[edit]

Intel and third parties have published benchmark results to substantiate performance leadership claims over other commercial, open-source and AMD compilers and libraries on Intel and non-Intel processors. Intel and AMD have documented flags to use on the Intel compilers to get optimal performance on Intel and AMD processors.^[14][15] Nevertheless, the Intel compilers have been known to use sub-optimal code for processors from vendors other than Intel. For example, Steve Westfield wrote in a 2005 article at the AMD website:^[16]

Intel 8.1 C/C++ compiler uses the flag -xN (for Linux) or -QxN (for Windows) to take advantage of the SSE2 extensions. For SSE3, the compiler switch is -xP (for Linux) and -QxP (for Windows). ... With the -xN/-QxN and -xP/-QxP flags set, it checks the processor vendor string—and if it's not 'GenuineIntel', it stops execution without even checking the feature flags. Ouch!

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The Danish developer and scholar Agner Fog wrote in 2009:^[17]

The Intel compiler and several different Intel function libraries have suboptimal performance on AMD and VIA processors. The reason is that the compiler or library can make multiple versions of a piece of code, each optimized for a certain processor and instruction set, for example SSE2, SSE3, etc. The system includes a function that detects which type of CPU it is running on and chooses the optimal code path for that CPU. This is called a CPU dispatcher. However, the Intel CPU dispatcher does not only check which instruction set is supported by the CPU, it also checks the vendor ID string. If the vendor string is 'GenuineIntel' then it uses the optimal code path. If the CPU is not from Intel then, in most cases, it will run the slowest possible version of the code, even if the CPU is fully compatible with a better version.

This vendor-specific CPU dispatching (function multi-versioning) decreases the performance on non-Intel processors of software built with an Intel compiler or an Intel function library – possibly without the knowledge of the programmer. This has allegedly led to misleading benchmarks,^[17] including one incident when changing the CPUID of a VIA Nano significantly improved results.^[18] A legal battle between AMD and Intel over this and other issues has been settled in November 2009.^[19] In late 2010, AMD settled a US Federal Trade Commissionantitrust investigation against Intel.^[20]

The FTC settlement included a disclosure provision where Intel must:^[21]

publish clearly that its compiler discriminates against non-Intel processors (such as AMD's designs), not fully utilizing their features and producing inferior code.

In compliance with this rule, Intel added an 'optimization notice' to its compiler descriptions stating that they 'may or may not optimize to the same degree for non-Intel microprocessors' and that 'certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors'. It says that:^[22]

Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice.

As reported by The Register^[23] in July 2013, Intel was suspected of 'benchmarksmanship', when it was shown that the object code produced by the Intel compiler for the AnTuTu Mobile Benchmark omitted portions of the benchmark which showed increased performance compared to ARM platforms.

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See also[edit]

• Intel Integrated Performance Primitives (IPP)
• Intel Data Analytics Acceleration Library (DAAL)
• Intel Math Kernel Library (MKL)
• Intel Threading Building Blocks (TBB)
• VTune Amplifier
• Intel Developer Zone (Intel DZ; support and discussion)

References[edit]

1. ^'Intel® oneAPI Toolkits DPC++/C++ Compiler Release Notes'. Intel. Retrieved 2020-12-17.
2. ^'Intel® oneAPI C++ Compiler Release Notes'. Intel. Retrieved 2020-12-29.
3. ^'Intel® System Studio 2016 for FreeBSD* Intel® Software'. software.intel.com. Retrieved 2018-03-15.
4. ^'Intel Debuts oneAPI Gold and Provides More Details on GPU Roadmap'. HPCwire. 2020-11-11. Retrieved 2020-12-17.
5. ^'Intel oneAPI DPC++ Compiler 2020-06 Released With New Features - Phoronix'. www.phoronix.com. Retrieved 2020-12-17.
6. ^Team, Editorial (2019-12-16). 'Heterogeneous Computing Programming: oneAPI and Data Parallel C++'. insideBIGDATA. Retrieved 2020-12-17.
7. ^'Khronos Steps Towards Widespread Deployment of SYCL with Release of SYCL 2020 Provisional Specification'. The Khronos Group. 2020-06-30. Retrieved 2020-12-17.
8. ^The Software Optimization Cookbook, High-Performance Recipes for IA-32 Platforms, Richard Gerber, Aart J.C. Bik, Kevin B. Smith, and Xinmin Tian, Intel Press, 2006
9. ^Intel C++ Compiler XE 13.0 User and Reference Guides
10. ^The pitfalls of verifying floating-point computations, by David Monniaux, also printed in ACM Transactions on programming languages and systems (TOPLAS), May 2008; section 4.3.2 discusses nonstandard optimizations.
11. ^This note is attached to the release in which Cilk Plus was introduced. This ULR points to current documentation: http://software.intel.com/en-us/intel-composer-xe/
12. ^Intel C++ Composer XE 2013 Release Notes[1]http://software.intel.com/en-us/articles/intel-c-composer-xe-2013-release-notes/
13. ^'Intel® Compilers Intel® Developer Zone'. Intel.com. 1999-02-22. Retrieved 2012-10-13.
14. ^[2]Archived March 23, 2010, at the Wayback Machine
15. ^'Archived copy'(PDF). Archived from the original(PDF) on 2011-03-22. Retrieved 2011-03-30.CS1 maint: archived copy as title (link)
16. ^'Your Processor, Your Compiler, and You: The Case of the Secret CPUID String'. Archived from the original on 2012-01-05. Retrieved 2011-12-11.
17. ^ ^ab'Agner`s CPU blog - Intel's 'cripple AMD' function'. www.agner.org.
18. ^Hruska, Joel (29 July 2008). 'Low-end grudge match: Nano vs. Atom'. Ars Technica.
19. ^'Settlement agreement'(PDF). download.intel.com.
20. ^'Intel and U.S. Federal Trade Commission Reach Tentative Settlement'. Newsroom.intel.com. 2010-08-04. Retrieved 2012-10-13.
21. ^'FTC, Intel Reach Settlement; Intel Banned From Anticompetitive Practices'. Archived from the original on 2012-02-03. Retrieved 2011-10-20.
22. ^'Optimization Notice'. Intel Corporation. Retrieved 11 December 2013.
23. ^'Analyst: Tests showing Intel smartphones beating ARM were rigged'.

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